Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application

The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. comparator works on deep sub-threshold supply VDD =0.3 V with common mode inputs. common-mode input range is VDD/2 minimum offset ranging between 8mV to 28mV. Thus circuit simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence has measured and tabulated by corresponding output voltage, power dissipation. But performance CMOS device not good when compared Fin Field-Effect Transistor (FinFET) device. leakage current more in devices while FinFET due control multi-Gates channel, reduced. This will improve consumption devices. results shows that inferior For Spice model were used this work. software project synopsis Hspice.